1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and a processing system and a semiconductor device, and more particularly, to a method for a semiconductor device, a processing system and a semiconductor device which are free of the risk of the occurrence of problems such as defective connections in the wiring.
2. Description of Related Art
In recent years, semiconductor elements have come to be required to employ an increasingly fine structure accompanying the higher levels of integration and higher performance of semiconductor devices. In addition, the wiring that interconnects semiconductor elements is also required to be increasingly fine.
However, in the manufacturing process of these semiconductor devices, as the semiconductor elements and wiring become increasingly fine, the forming accuracy of the pattern is being required to be increasingly high, and the allowable range for wiring defects and deficits is being required to be increasingly narrow.
Here, a conventional method for manufacturing a semiconductor device will be explained with reference to FIGS. 10A, 10B, and 11.
To begin with, as shown in FIG. 10A, N region 2 and P region 3 are formed on the surface of Si wafer (substrate) 1 by ion implantation or the like, and Sio2 film 4 is deposited on Si substrate 1 containing N region 2 and P region 3 by CVD or the like. The total surface area of the above N region 2 is about 1/1000 of the total surface area of P region 3.
Next, contact holes 5, extending to N region 2 and P region 3, are formed in this SiO2 film 4, and these contact holes 5 are filled with a metal such as W, Al or Cu to form plug electrodes 6.
Next, channel wiring grooves 7 are formed in the upper portion of plug electrodes 6, insulating film 8, composed of TiN or the like, is deposited over SiO2 film 4 including wiring grooves 7, and a wiring material in the form of Cu film 9 is deposited using plating technology.
Next, the unnecessary portions of insulating film 8 and Cu film 9 are removed by CMP in order to leave behind only insulating film 8 and Cu film 9 within channel wiring grooves 7, and as shown in FIG. 10B, channel wiring 10, also referred to as damascene wiring or embedded wiring, is formed on plug electrodes 6.
Furthermore, in order to form channel wiring 10 using a method other than CMP such as dry etching, insulting film 8 and Cu film 9 within channel wiring grooves 7 should be left behind using a resist and the like as a mask, and the other unnecessary portions of insulating film 8 and Cu film 9 should be removed by dry etching.
As a result, semiconductor substrate 11 is fabricated on which channel wiring 10 is exposed.
Next, a cleaning step is carried out on semiconductor substrate 11 obtained in this manner using the cleaning system shown in FIG. 11.
The composition of this cleaning system is composed of a wafer holder 15, which holds semiconductor substrate 11 and is able to rotate using a vertical rotating shaft (not shown) as its axial center, a nozzle 16, which supplies a conductive cleaning chemical (or pure water) to semiconductor substrate 11, and a light source 17, which radiates light having a wavelength of 500 nm or less onto a region containing semiconductor substrate 11.
In this cleaning system, the surface of semiconductor substrate 11 is cleaned by supplying cleaning chemical (or pure water) onto its surface while rotating semiconductor substrate 11 in the state in which the wavelength of the light radiated onto semiconductor substrate 11 is 500 nm or less.
In addition, a processing method for a semiconductor substrate has been proposed in which the semiconductor substrate is processed in a state in which light having energy equal to or greater than the band gap (1.12 eV or more in the case of silicon) is shielded or shaded to below a prescribed intensity (brightness) so as not to be irradiated onto the substrate surface (refer to, for example, Japanese Unexamined Patent Application, First Publication, No. Hei 11-251317).
FIG. 14 is a cross-sectional view showing the Cu wiring of a semiconductor substrate that has undergone prescribed processing according to this processing method. In this drawing, the Cu wiring of a semiconductor substrate is composed of wiring 21 connected to a diffusion layer, an insulating film 22 comprised of a silicon oxide film or nitride film, etc., a normally polished W plug 23, a TiN barrier 24, and normally polished Cu wiring 25.
FIG. 15 is a drawing showing the wiring resistance of Cu wiring formed in this manner as measured in a pattern having a length of 1 mm. In the method of the prior art (A in the drawing), although the wiring resistance increases remarkably due to the occurrence of deficits in a portion of the wiring if the width becomes 0.2 μm or less, in the case of this processing method (B in the drawing), wiring resistance is equal to or less than low resistance Cu wiring until the width approaches 0.1 μm.
However, in the case of the cleaning method described above, during cleaning of semiconductor substrate 11 by the conductive cleaning chemical (or pure water), there was the problem of the selective occurrence of wiring defects in channel wiring 10 on the N region 2 side due to galvanic effects caused by photoexcitation.
The reason for this is that, in the case light is radiated from light source 17 onto this semiconductor substrate 11, electromotive force is generated in the PN junction within semiconductor substrate 11 due to galvanic effects caused by photoexcitation. As a result, Cu2+ migrate from channel wiring 10 on the P region 3 side towards channel wiring 10 on the N region 2 side, and as shown in FIGS. 12 and 13, the surface of Cu precipitated on channel wiring 10 on the N region 2 side oxidizes resulting in the formation of a highly resistive layer 12 having for its main component CuO on channel wiring 10 on the N region 2 side.
In this cleaning step, although it is ideal to prevent light from radiating onto the PN junction in semiconductor substrate 11, when detecting its presence or inspecting film thickness during transfer of semiconductor substrate 11, a certain quantity of light unavoidably ends up radiating onto semiconductor substrate 11, thereby making it difficult to eliminate wiring defects in channel wiring 10 on the N region 2 side.
In addition, in the above processing method, light that is shielded or shaded to below a prescribed intensity (brightness) has a wavelength corresponding to a wavelength range in which the semiconductor is not excited, and is a wavelength of 1.2 μm or less corresponding to the band gap of silicon.
For example, in a photodiode of an Si-p+-i-n structure having a broad i layer (intrinsic region) shown in FIG. 16, this corresponds to the region in which efficiency becomes 0 at 1.2 μm or less. Thus, current does not flow through this region.
In this processing method, however, since light having a visible wavelength (380–800 nm) is shielded or shaded to below a prescribed intensity (brightness), the wafer and the like cannot be confirmed visually. Since wafer sensors and the like using a wavelength of 1 μm or less are typically installed in silicon wafer transport systems for use as sensors that detect the presence of wafers, work is unable to proceed in a state in which light having a wavelength of 1.2 μm or less is not present in the device.